As integrated circuits (IC) become increasingly dense and complex, all aspects of design, including custom and synthesized design, design verification and testing are becoming more and more difficult. The immensity of the data and the complex interrelationships among the various aspects of design including the design data, technology, and test, make it extremely difficult for IC designers to complete a design with confidence that it will function at the intended performance, and be manufacturable and reliable. Design aids that enable the visualization of circuit functionality, simulated under various operating conditions, process conditions, and electrical input conditions, that are interactive and cross-probeable with the device and circuit elements of the design views would greatly enhance the ability to create robust designs more effectively and in less time. This invention addresses this need by providing a system and method of visualizing the electrical activity and/or logical activity of an IC. It is easy to use and interpret, and the various design, simulation, and hardware data views contain parameterized, cross-probeable and interrelated content, at the transistor, gate, or circuit level. Here, the term “visualization” is used broadly, and include animation (for example, slow motion movies) with or without audio enhancement, plots of interrelationships between various dependent and independent variables, and also includes tactile outputs to assist the visually impaired.
A particular embodiment that relates a simulated view to a photon emission view and provides comparative visualizations of each, is disclosed herein. This particular embodiment relates to the commonly owned patent application Ser. No. 09/406,664 entitled METHOD FOR VLSI SYSTEM DEBUG AND TIMING ANALYSIS filed herewith, the disclosure of which is incorporated herein by reference. This patent application Ser. No. 09/406,664 provides a means by which to characterize internal IC switching activity by measuring and presenting photon emission data according to the technology described in the commonly owned and co-pending U.S. patent application Ser. No. 08/683,837, entitled NONINVASIVE OPTICAL METHOD FOR MEASURING INTERNAL SWITCHING AND OTHER DYNAMIC PARAMETERS OF CMOS CIRCUITS, filed Jul. 18, 1998, the disclosure of which is also incorporated herein by reference.
A feature of simulated picosecond imaging circuit analysis (PICA) is that any test or instruction set sequence may be applied to the circuit under investigation and will lead to observable results. This is contrasted to the present state of PICA measurements. Care must be taken to keep the PICA measurement loop short, and the test loop must be exercised repeatedly. This is because of the low level of emitted light in the photoluminescence process. This low light level, and the finite duration of the test loop make PICA measurement aquisition times slow. Thinning of the chip further increases the complexity of preparation of test. The simulation, however, is not limited by the low probability for photoluminescence, and any arbitrary test sequence or instruction sequence may be applied and the reaction visualized. The requirement to repeatedly exercise the circuit disappears for the case of PICA simulation. Simulation is also quick compared to measurement. Simulation is also amenable to characterization of the design prior to building the device. Hence, PICA simulation opens up many opportunities for improving designer productivity which have been heretofore unavailable by other means. An example of such a newly enabled application is a test coverage checker which produces output in a visual, intuitive manner.
The invention also relates to the problem of expressing causal relationships in a manner which is easily and intuitively interpreted. For example, circuit designers often analyze simulated circuit activity by plotting voltage waveforms on a common time base to visualize the causal relationships, such as shown in FIG. 1 for an inverter chain. The dotted lines pointing from one waveform to the next indicate the causal order of switching events. These relationships can be expressed in terms of a “sequence graph”. FIG. 2 shows an example of a sequence graph, 12, for the invertor chain. The net names (1, 2, 3, etc.) are indicated at the nodes, as are the corresponding waveforms (a, b, c, etc.). The arrows connecting the nodes indicate the causal relationship between the voltage behaviors at the nets.